TSMC’s chairman, Mark Liu, not too long ago confirmed that the restricted availability of compute GPUs for AI and HPC purposes stems from constraints of their chip-on-wafer-on-substrate (CoWoS) packaging capability.
It’s forecasted that this deficit will proceed for about 18 months as a result of rising demand for generative AI purposes and the measured growth of CoWoS capability at TSMC.
Talking at Semicon Taiwan, Mark Liu clarified, “The scarcity pertains to our CoWoS capability, not AI chips. We presently cannot fulfill all of our buyer calls for, however we’re working in direction of addressing roughly 80% of them. That is seen as a transient part. We anticipate alleviation after the expansion of our superior chip packaging capability, roughly in a single and a half years.”
TSMC manufactures key AI processors, amongst that are Nvidia’s A100 and H100 compute GPUs. These GPUs, important in instruments like ChatGPT, discover main software in AI knowledge facilities. Corresponding to merchandise from AMD, AWS, and Google, these processors use HBM reminiscence, important for top bandwidth and efficient functioning of expansive AI language fashions, and CoWoS packaging. This elevates the demand on TSMC’s superior packaging infrastructure.
Liu famous the demand for CoWoS had a shocking threefold improve year-over-year earlier this 12 months, ensuing within the current provide bottlenecks. TSMC is conscious of the surging demand for generative AI instruments and the related {hardware}. Therefore, it is hastening the augmentation of CoWoS capability to cater to compute GPUs, devoted AI accelerators, and processors’ wants.
The corporate is now integrating extra CoWoS tools in its present superior packaging vegetation. This effort will take time, with expectations to double its CoWoS capability solely by the top of 2024.
TSMC additionally not too long ago introduced a $2.9 billion funding in a brand new facility centered on superior chip packaging close to Miaoli, Taiwan, which highlights the corporate’s technique to satisfy the superior packaging demand industry-wide and acknowledges the position of superior chip packaging in the way forward for semiconductors.
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