Article By : XConn Applied sciences
XConn Applied sciences demonstrated the entire Compute Categorical Hyperlink (CXL) 2.0 ecosystem, from end-to-end, eventually week’s Intel Innovation occasion.
XConn Applied sciences demonstrated the entire Compute Categorical Hyperlink (CXL) 2.0 ecosystem, from end-to-end, on the latest Intel Innovation held September 19-20 in San Jose Conference Middle. The demonstration showcased, for the primary time, the CXL 2.0 specification in motion, from host to machine, for the flexibility to scale as much as 15TB to help “Only a Bunch of Reminiscence” (JBOM) purposes wanted by HPC and AI environments.
The XConn Apollo Change, which helps CXL 2.0, interoperates with Samsung DRAM Reminiscence Expander supporting CXL, Micron CZ120 reminiscence growth module, Reminiscence eXpander Controller (MXC) for CXL from Montage Expertise, and the high-speed CPU interconnect (CMM) for CXL from Sensible Modular Applied sciences. The Apollo change is the trade’s first and solely hybrid CXL 2.0 and PCIe Gen 5 interconnect answer. On a single 256-lane SoC, the XConn change affords the trade’s lowest port-to-port latency and lowest energy consumption per port in a single chip at a low whole price of possession.
“The XConn demo throughout Intel Innovation is the primary true realization of the CXL 2.0 specification in motion validating the outstanding potential of CXL because it will increase reminiscence utilization effectivity and gives true reminiscence capability on demand,” stated Gerry FanCEO, XConn. “With our Apollo change, environments can really reap the benefits of CXL 2.0 to exponentially scale to help even essentially the most reminiscence intensive HPC and AI purposes.”
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The Apollo change is a hybrid interconnect answer supporting CXL 1.1 and a couple of.0 in addition to PCIe Gen 5 specs in the identical system. This flexibility affords system designers unprecedented flexibility to help each software want with a single chip.
“We’re delighted at XConn’s contribution to the CXL ecosystem,” stated Jim Pappasdirector of Expertise Initiatives Intel Company. “Their end-to-end CXL 2.0 demonstration underscores the dramatic potential of CXL to fulfill the growing efficiency calls for of next-generation knowledge facilities.”
“Samsung has collaborated with XConn within the improvement of superior CXL options and is actively concerned within the CXL 2.0 ecosystem that’s architecting new reminiscence capability growth options that optimize price and efficiency for tomorrow’s most demanding purposes,” stated Jangseok (JS) Choi, vice chairman of New Enterprise Planning Workforce at Samsung Electronics. “Along with XConn, we’re serving to the trade’s use of CXL turn out to be realized.”
“Micron and XConn have been increasing the relevance of the XConn CXL 2.0 change options to rising purposes,” stated Siva Makineni, vice chairman of Micron’s Superior Reminiscence Techniques. “Our continued collaboration to guide modern applied sciences underpin the influence CXL 2.0 may have in next-generation computing methods.”
“We’re happy to see XConn carry collectively a whole ecosystem of CXL 2.0 innovators as an example the worth of CXL for the way forward for processing,” stated Larry Carrpresident, CXL Consortium.
The XConn Apollo XC50256, which options full help for CXL 2.0, is backwards suitable with CXL 1.1 and helps PCIe Gen 5 in hybrid mode, is obtainable now. With 256-lanes, Apollo additionally helps PCIe Gen 5 mode for AI-intensive purposes and is a key part for the long run Intel Xeon processors in JBOG and JBOA environments.
