Samsung Electronics Co. will launch low latency vast (LLW) DRAMs subsequent 12 months, designed to enhance the facility effectivity of synthetic intelligence purposes by 70% greater than that of standard DRAMs, the corporate mentioned at its annual buyers discussion board final week.
LLW DRAMs will turn out to be its flagship, next-generation chips and be embedded into AI gadgets akin to prolonged actuality headsets. Samsung goals to beef up synthetic intelligence chip foundry gross sales to about 50% of its complete foundry gross sales in 5 years.
The brand new AI chips will improve knowledge processing pace and capability by growing the variety of enter/output terminals (I/O) in a semiconductor circuit, in contrast with current DRAMs.
3D PACKAGING
Subsequent 12 months, the world’s No. 1 reminiscence chipmaker will unveil a complicated three-dimensional (3D) chip packaging know-how, together with essentially the most superior 3.5D packaging, the corporate mentioned in the course of the IR occasion.
It will increase the processing pace and knowledge processing capability of digital gadgets by stacking processors such because the central processing unit (CPU) and graphics processing unit (GPU) vertically with high-bandwidth reminiscence (HBM) chips.
3 NM PROCESS
Samsung additionally will additional sharpen its 3-nanometer chip processing know-how, at present the business’s smallest and most superior course of node, to be appropriate for AI purposes.
Final 12 months, it started the mass manufacturing of three nm chips for fabless shoppers as a worldwide first and forward of Taiwan’s TSMC Co.
Earlier this 12 months, Samsung was mentioned to have considerably superior the manufacturing yields of its first-generation 3 nm course of know-how to “an ideal stage.”
“We are able to enhance (reminiscence chips’) efficiency by 2.2 instances each two years,” mentioned Jeong Ki-bong, vice chairman of Samsung Foundry, the foundry semiconductor enterprise of Samsung Electronics, informed buyers on the IR occasion.
GDP STRATEGY
On the buyers discussion board, Samsung introduced the initials of GAA, dram and packaging, or GDP, because the key phrase for its new technique.
GAA, brief for gate-all-around, reduces the leakage present of processors with a circuit width of three nm or beneath. It’s Samsung’s key structure to develop next-generation DRAMs and packaging know-how.
The three nm know-how is the primary course of node on which Samsung utilized its first-generation GAA construction transistors.
IN COLLABORATION WITH TESLA
Samsung is working with Tesla Inc. to develop the EV maker’s next-generation Full Self-Driving (FSD) chips for Degree-5 autonomous driving autos.
Samsung not too long ago employed YoonJung Ahn, a design head at Waymo, Alphabet’s autonomous driving know-how unit, as government vice chairman to steer the design administration middle.
The chipmaker additionally plans to develop a 4 nm AI accelerator, a high-performance computing machine used to course of AI workloads.
Based on market analysis agency Omdia, the AI semiconductor market, estimated at $55.3 billion this 12 months, is anticipated to achieve $112 billion by 2027.
Write to Jeong-Soo Hwang and Ik-Hwan Kim at hjs@hankyung.com
Yeonhee Kim edited this text
