Lengthy, way back, on the flip of the millennium, two champions of configurable processor IP – ARC and Tensilica – battled for dominance in that area with distinctive processor ISAs and customized instruments to assist in creating software-development software chains for his or her configurable processors. Synopsys purchased ARC in 2011, and Cadence purchased Tensilica a few years later. Quick ahead a decade and all of a sudden, RISC-V has one way or the other validated the idea of configurable processors. Consequently, many firms with proprietary processor ISAs have jumped on the RISC-V bandwagon as its ecosystem gathers momentum. For instance, Intel introduced the event of a 3rd NIOS-V smooth processor core for its FPGAs earlier this 12 months (see “Intel Heats Up and Expands its Agilex FPGA household”) and AMD slipstream launched the MicroBlaze V 32-bit modular and configurable RISC-V smooth processor core to its early entry FPGA builders in November. Now, Synopsys has introduced the evolutionary department of its ARC processor IP into the RISC-V area with a trio of latest ARC-V configurable processor cores.
Synopsys has sectioned its ARC-V core choices into three segments. The low-end, low-power, 32-bit ARC-V RMX processor IP is scheduled to be out there in Q2 of 2024. This section affords cores with 3- and 5-stage pipelines, and an elective DSP. The 32-bit Synopsys ARC-V RHX processor cores serve real-time purposes and have a dual-issue superscalar pipeline, {hardware} virtualization, and a purposeful security (FUSA) hybrid mode the place a pair of ARC-V RHX processors can run in lockstep for ASIL D security purposes or in a twin processor mode for ASIL B security purposes. The 64-bit ARC-V RPX host processor cores are just like the RHX variants however are 64-bit as an alternative of 32-bit implementations. Further ARC-V RPX capabilities embrace a cache-coherent interconnect that allows the design of processor clusters with as many as sixteen processor cores and clusters of processor clusters. The ARC-V RHX and RPX processor cores are scheduled to be out there within the second half of 2024.
All the ARC-V processor cores share the identical MetaWare software chain. ARC acquired MetaWare about 25 years in the past and adopted its software program improvement instruments for its configurable processor IP. Those self same instruments, a lot advanced, nonetheless help the present configurable ARC IP cores and have been prolonged to help the brand new ARC-V cores. As a result of all RISC processor cores share many similarities reminiscent of a {hardware} instruction decoder, pipelined execution, giant register recordsdata, and a load-store structure, Synopsys was ready to make use of the present equipment for the ARC configurable processor cores and developed the ARC-V cores by altering the processor’s instruction decoder, pipeline, and microarchitecture.
Consequently, present clients for the unique ARC processor cores can merely recompile their code for the brand new ARC-V cores. The MetaWare software chain is explicitly conscious of processor configurability and accepts recordsdata from the ARC processor configurator (wittily named ARChitect) to routinely configure the software chain to generate code for the processor extensions. This similar software program software chain additionally helps the ARC vector DSP and neural processor.
The RISC-V processor core market is pretty crowded nowadays with gamers together with Andes, Codasip, Creativeness, MIPS, Rivos, SiFive, Tenstorrent, Codasip, XMOS, and Ventana. However, Synopsys has jumped into this market with each toes by signing up as a Premiere member of RISC-V Worldwide, which supplies the corporate a seat on the group’s Board of Administrators, and has joined the RISC-V Technical Steering Committee, which permits Synopsys to take part within the definition of future RISC-V structure requirements.
The crowded RISC-V processor core market prompts two questions in regards to the Synopsys entry. What attracted Synopsys to the RISC-V melee, and the way will Synopsys differentiate its processor cores among the many many choices? Matt Gutierrez, Group Director of Advertising and marketing for Processor and Security IP and Instruments at Synopsys solutions the primary query succinctly by saying, “What’s enticing about RISC-V is the momentum of the ecosystem.” When requested if Synopsys had joined the RISC-V Software program Ecosystem (RISE) Mission – a consortium of firms concerned with RISC-V ecosystem improvement, together with Andes, Google, Intel, Creativeness Applied sciences, MediaTek, Nvidia, Qualcomm Applied sciences, Crimson Hat, Rivos, Samsung, SiFive, T-Head, and Ventana – Gutierrez replied, “No, however we’re definitely conscious of it.” I’ll take that to be a strong “Not but, one factor at a time” form of reply. There’s the matter of how the Synopsys MetaWare instruments match into the higher RISC-V ecosystem to work out first.
As for the second query relating to the differentiation that Synopsys will have the ability to provide the RISC-V neighborhood, John Koeter, Senior VP of Advertising and marketing and Technique at Synopsys, was not perplexed. Since Synopsys jumped into the IP market greater than 20 years in the past, IP has change into “25% of Synopsys,” stated Koeter. Not like many of the competing RISC-V core distributors, Synopsys is a broad-spectrum IP provider with choices that embrace logic libraries, embedded recollections, analog IP, wired and wi-fi interface IP, safety IP, embedded processors, and subsystems. Processor cores are solely a fraction of the IP blocks within the firm’s portfolio. As well as, the corporate’s IP helps many various course of nodes at a number of silicon foundries.
As well as, Synopsis has robust ties to SoC and system design homes by means of its EDA software choices, and IP usually comes alongside for the experience in main corporate-wide EDA and IP purchases. The buying determination for a RISC-V core may be very completely different when it’s part of an total EDA and IP contract. As well as, Gutierrez factors out that, due to the tie-in with its EDA instruments, Synopsys can present a reference design circulate for its ARC-V processor cores that’s been validated with Synopsys EDA instruments. Put all of those collectively and it might seem that Synopsys will rapidly change into a heavyweight provider within the RISC-V IP market.
The transfer into the RISC-V area by Synopsys begs the query about plans by the opposite main EDA and IP vendor: Cadence. It’s been 20 years since Cadence acquired Tensilica, and a transfer to convey its Tensilica IP into the RISC-V camp in a manner that intently resembles the trail that Synopsys is taking with its ARC-V cores appears an apparent response, simply as Cadence acquired Tensilica two years after Synopsys acquired ARC. Cadence is definitely conscious of RISC-V. The corporate printed a weblog about RISC-V processors final 12 months, and its clients are virtually definitely working RISC-V processor cores from different distributors by means of Cadence’s EDA instruments already. Very doubtless, it’s solely a matter of time earlier than Cadence jumps on the RISC-V bandwagon as properly.
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