RISC-V server chip designer Ventana Micro Techniques has pushed out its second era Veyron processor, squeezing in additional cores and the power for purchasers so as to add customized accelerator bits to a bespoke system-on-chip (SoC) blueprint.
Ventana launched its first era package, the Veyron V1, finally 12 months’s RISC-V Summit, focusing on clients in search of a datacenter-class processor that might declare efficiency similar to different architectures in the marketplace.
The Cupertino RISC-y slinger mainly sells its product within the type of a ready-made multi-core chiplet, with the concept clients reminiscent of hyperscalers can mix a number of chiplets in an SoC to satisfy their particular processing necessities.
{Hardware} hacker: Walling off China from RISC-V ain’t such a terrific concept, Mr President
READ MORE
In keeping with Travis Lanier, Ventana’s VP of selling & product, the Veyron V2 incorporates the entire updates within the RISC-V specs, in addition to aligning with Common Chiplet Interconnect Specific (UCIe) as the usual for connecting chiplets collectively, relatively than the Bunch of Wires (BoW) system seen within the V1.
Veyron V2 helps the RVA23 function set, which is the RISC-V instruction set profile for this 12 months, and implements the RISC-V Enter-Output Reminiscence Administration Unit (IOMMU) specs.
The IOMMU specification being ratified “was a giant deal within the RISC-V house,” in line with Lanier. “Anytime you have got a digital machine, and also you need to have direct entry to one in every of your PCIe gadgets, you do not have to do all of the software program overhead to change it round, so this can be a crucial function for datacenter purposes,” he defined.
It’s also a key a part of RISE compatibility, he claimed, which is an trade venture geared toward constructing the mandatory utility ecosystem round RISC-V.
Ventana has additionally taken benefit of the RISC-V Vector Extension specs so as to add a vector processing unit to its cores. That is 512 bits huge, and in addition options what Ventana calls AI Matrix Extensions, which Lanier claimed will “assist considerably with a few of these generative AI or inference workloads.”
As well as, every Veyron V2 chiplet now helps as much as 32 cores as a substitute of 16 within the earlier era, whereas the clock pace and the general variety of cores stay at 3.6GHz and as much as 192 cores. The scale of the caches has additionally elevated, to 1MB of L2 per core and as much as 128MB of shared cluster-level L3 cache.
The entire modifications in Veyron V2 translate to a efficiency enhance of virtually 40 p.c over the earlier era, Lanier claimed.
Pedal to the metallic
Veyron V2 additionally helps DSA, or Area Particular Acceleration, a functionality that permits the shopper so as to add bespoke accelerator chiplets to their SoC. That is geared toward hyperscale clients that will want to enhance particular workloads within the datacenter, in line with Lanier, reminiscent of compression and encryption, TCP offload processing in networks, or key/worth processing in databases.
These accelerator chiplets are supported by the Veyron cores through customized directions that Ventana has added, which is without doubt one of the supposed huge promoting factors of the entire RISC-V structure.
On this case, the customized directions allow software program to name the accelerator, in what may very well be seen as an echo of the best way Intel processors had directions to name the floating level unit (FPU) again within the days when one in every of these was an non-compulsory separate chip.
One other declare for Veyron V2 is that it has been designed to be extra proof against aspect channel assaults, such because the Spectre and Meltdown flaws that probably allowed information to be stolen from a server’s reminiscence.
Lanier was cagey about particularly what this implies, however emphasised that it doesn’t imply such an assault is inconceivable with Veyron chips, simply that the V2 has been designed with information of the best way these assaults are carried out.
“We had the luxurious of beginning our design, in spite of everything these got here to gentle,” he stated, including that the price to datacenter clients of operating software program patches or mitigations to affected servers can usually be a ten and even 20 p.c hit on efficiency.
The Veyron V2 silicon is deliberate to be obtainable someday within the second half of 2024.
For final 12 months’s V1, the chiplets had been designed for TSMC’s 5nm manufacturing node. This 12 months, Ventana is just not specifying which foundry is producing the V2 chiplets, although stated they are going to be made utilizing a course of smaller than 5nm. ®
